1. Field of the Invention
The present invention relates to a semiconductor process of integrated circuit devices. More particularly, the present invention relates to a method for forming trench isolation regions on a semiconductor substrate.
2. Description of the Prior Art
The art of isolating semiconductor devices becomes one important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology. With increasing densities of up to hundreds of thousands of devices on a single chip, improper isolation among devices will cause current leakage. These current leakages can consume significant amounts of power. In addition, improper isolation between devices can exacerbate latchup, which can damage the circuit temporarily or permanently. Still further, improper isolation can result in noise margin degradation, voltage shift or crosstalk.
In MOS technology, isolation is usually practiced by forming isolation regions between neighboring active regions. Typically, an isolation region is formed by ion-implanting a channel stop layer of polarity opposite to the source electrode and the drain electrode of the integrated circuit device, and growing a thick oxide, often referred to as field oxide (FOX). The channel stop and the FOX cause the threshold voltage in the isolation region to be much higher than those of the neighboring active devices, making surface inversion not likely to occur under the field oxide region.
The local oxidation of silicon (LOCOS) method is widely used to isolate active regions in silicon. In LOCOS technology, a silicon nitride layer is used as an efficient oxidation mask which prevents the oxidants from reaching the silicon surface covered by silicon nitride. In addition, the silicon nitride layer oxidizes very slowly compared to silicon. However, direct deposition of silicon nitride on silicon can cause stress induced defects when the structure is subjected to oxidation at elevated temperature. These defects can be considerably reduced by forming a thin (100-500 angstroms) pad oxide layer between the silicon and the silicon nitride. The pad oxide reduces the force transmitted to the silicon by relieving the stress. This arrangement thus acts as a buffer which cushions the transmission of stress between the silicon and the silicon nitride.
Unfortunately, the pad oxide layer provides a lateral path for oxidation of silicon. This lateral extension of oxidation through pad oxide is frequently referred to as a xe2x80x9cbird""s beakxe2x80x9d because of its form. The extent of the bird""s beak can be reduced by decreasing the thickness of the pad oxide, which, however will cause more stress induced defects from the above silicon nitride layer. Therefore, the thickness of the pad oxide and the silicon nitride layer must be optimized to minimize the extent of the bird""s beak without generating defects.
Beside bird""s beak effect, another important limitation is the sharp decrease in the field oxide thickness as the isolation spacing is reduced below 1 micrometer. The narrower the opening is, the thinner the field oxide will be. This effect is frequently called field oxide thinning effect, and is more serious for deem sub-micron semiconductor devices. The aforementioned bird""s beak effect, the local field oxide thinning effect, and the stress-induced silicon defect are discussed in some references, such as that by Andres Bryant et al., xe2x80x9cCharacteristics of CMOS Device Isolation for the ULSI Age,xe2x80x9d IEDN Tech. Dig., 1994, pages 671-674 which is hereby incorporated by reference.
Several methods in the prior art have been designed for improving the LOCOS isolation process to minimize the bird""s beak. For example, a nitride-clad LOCOS (NCL) isolation is disclosed, for example, by J. R. Pfiester et al., xe2x80x9cNitride-Clad LOCOS Isolation for 0.25 xcexcm CMOS,xe2x80x9d VLSI Tech. Symp. Dig., 1993, pages 139-140 which is hereby incorporated by reference. Unfortunately, the NCL process usually causes some defects at the edge of the isolation region.
Another isolation method, called polysilicon buffer LOCOS (PBL) isolation, is also used to overcome the disadvantages of the conventional LOCOS method. See the reference by J. Nagel et al., xe2x80x9cStress-induced Void Formation in Interlevel Polysilicon Films during Polybuffered Local Oxidation of Silicon,xe2x80x9d J. Electrochem. Soc., vol. 140, 1993, pages 2356-2359 which is hereby incorporated by reference. One of the disadvantages induced from the PBL method is the formation of voids or pits.
Other isolation methods are also available. For example, the sealedinterface local oxidation (SILO) process uses an additional thin silicon nitride over the silicon substrate followed by forming a pad oxide layer and then a thick silicon nitride layer. The SILO process can reduce the bird""s beak, but at the expense of generating more stress, more crystal defects, and higher leakage currents.
Another improved LOCOS method, called buried oxide (BOX) process, has been devised which uses an aluminum mask to etch a silicon groove and then subsequently remove a plasma deposited silicon dioxide layer. The BOX process can effectively reduce the bird""s beak, but at the expense of manufacture complexity.
The trench isolation process, or the shallow trench isolation (STI) process, is another isolation process proposed especially for semiconductor chips with high integration. A trench region is formed in the semiconductor with a depth deep enough for isolating the devices or different wells. In general, a trench is etched and refilled with insulating materials in the trench isolation process. The refilled trench regions are developed for the application in the very large scale integration (VLSI) and ultra large scale integration (ULSI) level. In addition, capacitors can also be formed within the trench by filling both insulating and conductive materials sequentially for the application of forming memory cells.
The conventional LOCOS isolation process suffers the problems like large bird""s beak, local field oxide thinning effect, and stress-induced silicon defects. In the aforementioned article titled xe2x80x9cCharacteristics of CMOS Device Isolation for the ULSI Agexe2x80x9d by A. Bryant et al. (in IEDM Tech. Dig., p. 671, 1994), different isolation processes are investigated. They reviewed how LOCOS and STI isolation are being improved to meet the scaling requirements. The scalability of LOCOS for sub-half-micrometer CMOS technologies is a widely identified question. The issues like lateral extent of the LOCOS bird""s beak, non-planarity, thinning, and stress-induced silicon defects are addressed in their work. It is concluded that future CMOS technology will require an effective device isolation method that provides abrupt transitions to active device regions with a minimum impact on device characteristics or topography.
At 1996, S. E. Kim et al. disclosed a LOCOS technology in the work xe2x80x9cNitride Cladded Ploy-Si Spacer LOCOS (NCPSL) Isolation Technology for the 1 Giga Bit DRAMxe2x80x9d (in IEDM Tech. Dig., p. 825, 1996). The limitation of the conventional LOCOS technology with the scaling down of the devices is illustrated. Fully recessed LOCOS is one solution to the problem. However, simply recessing the field regions before field oxidation brings about excessive bird""s beak penetration. They merged the concept of RPSL (Recessed Poly-Si Spacer LOCOS) and RNSL (Recessed Nitride Spacer LOCOS) to reduce the bird""s beak length while maintaining the smooth edge profile by employing selective SiN deposition on poly-Si spacer.
Although with better isolating characteristics than the LOCOS process, the trench isolation process is suffered from a large defects induced by dry etching and sharp trench corner effects. In the work of P. C. Fazan and V. K. Mathews (xe2x80x9cA Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMsxe2x80x9d, in IEDM Tech. Dig., p. 57, 1993), the replacement of the LOCOS-based isolation schemes with the STI process is disclosed. STI provides a planar surface and a fully recessed field oxide, does not suffer from field oxide thinning, and can easily be scaled down for 1 to 4 Gb DRAM applications. However, STI also requires a much more complicated planarization procedure and carries the devices reverse narrow width effects. A trench isolation process combining tapered trench sidewalls, a trench reoxidation, a vertical B field implant, a CMP-only planarization, and disposable spacers to smooth the trench comers, is proposed in the work.
For solving the trench comer effects, many methods and structures have been developed. U.S. Pat. No. 5,521,422 to J. A. Mandelman is an example. In the work xe2x80x9cCorner Protected Shallow Trench Isolation Devicexe2x80x9d, a semiconductor structure to prevent gate wrap-around and corner parasitic leakage is proposed. A sidewall structure around the trench region is formed to solve the problems induced in the planarization process. The problems of the corner leakage and the recessed isolation insulator adjacent the corner is solved by the structure in their work with the additional sidewall structure.
In accordance with the present invention, a method is provided for forming trench isolation regions for integrated circuits. The trench isolations provides improved comer rounding and reduced undesired stress effects.
The method for forming an isolation region in the present invention mainly includes the following steps. At first, a pad layer is formed on a semiconductor substrate and an oxidation masking layer is formed on the pad layer. The pad layer is provided to relieve the stress from the oxidation masking layer. The oxidation masking layer, the pad layer, and the substrate are then patterned to form trenches in the substrate. The pad layer is removed laterally to form undercut structures under the oxidation masking layer. A doped layer is conformably formed on the oxidation masking layer, the undercut structures of the pad layer, and the substrate in the trenches.
Next, a thermally oxidizing step is carried out to oxidize the doped layer to form an oxidized layer conformably on the oxidation masking layer, the undercut structures of the pad layer, and the substrate in the trenches. A dielectric layer is formed over the substrate to fill up the trenches and cover over the pad layer and the oxidation masking layer. The dielectric layer is planarized downward to portions of the oxidation masking layer. Finally, the oxidation masking layer and the pad layer are removed.
In the preferred embodiments, the doped layer is selected to have a greater oxidation resistance than the pad layer. In addition, the doped layer is preferably a material which generates less stress than the oxidation masking layer.